As the semiconductor industry makes improvements in transistor density, one of the challenges is controlling manufacturing variation. Control of polysilicon (poly) critical dimension (CD) is one of the critical requirements in the processing of an integrated circuit (IC), due to the poly CD affect on transistor performance. Poly CD control typically must scale for the new technology to keep the percentage variation of the channel length constant. These critical requirements often make poly the first layer to require new patterning solutions and design rules.
A known method of enhancing CD control during photolithography and etching processes is to insert dummy poly lines during the layout process. As well as aiding patterning, the dummy poly lines aid the subsequent etch process. Different consumptions of etchants due to different pattern density lead to etch skew between dense and isolated patterns. Typically, all available etchants in areas with low density are consumed rapidly, and thus the etch rate drops off significantly. To reduce this etch skew, dummy poly lines may be inserted adjacent to the primary pattern with specific spacing. Furthermore, dummy poly lines may be placed outside of active-layer regions. Dummy poly lines require correct placement to make the printability of resist and the etch processes better.
Design rules specify the constraints on a device layout. For example, design rules typically specify the smallest width feature that may be used in a layout, for example, poly line width and channel length. Further, design rules specify the smallest spacing between features that may be used to ensure that the features do not short. The pitch of regularly spaced feature lines is the distance from the first side of the first line to the first side of the next line. Thus, the pitch is the feature line width plus the intermediate space between feature lines.
Early prior art layout had loose design rules that allowed random combinations of poly widths, spaces and device orientation. As devices shrunk, the design rules changed to accommodate the use of optical proximity correction (OPC), and/or phase shift masks (PSM), and/or off axis illumination (OAI). A change in illumination technology, such as OAI to achieve minimum line width and minimum space may not allow the same scaling for wider lines, or it may make scaling different in the X and Y directions. These tools and methods work best when the layout is predictable and there are no hotspots caused by the use of unexpected combinations of design rules.
In some processes, for example if OAI is used, the photolithography process is chosen to enhance the characteristics of the most common pitches in the layout. When optimized for one pitch, the minimum or the most commonly used pitch in the design, there may be other pitches for which the photolithographic processes lead to a poor response and hence a small depth of focus/process window. These problems have lead to the development of layout cells that have a consistent poly pitch oriented in a single direction across device cells. These cells are termed default or default cells. Therefore, the design rules changed wherein poly layout rules based upon restricting poly line width, poly spacing, and orientation were implemented.
However, some circuits cannot meet the poly pitch requirement; for example, footer, header, lever shifter, and decoupling cells may require a different poly pitch. A circuit designer using a library of default poly pitch cells may need to place a non-default poly pitch cell or cells within a device layout. Confusion and device layout difficulties may arise as the circuit designer attempts to implement a non-default cell or cells into an otherwise default cell device.
What is needed then, is a new integrated circuit structure and system of accommodating mixed poly pitch cells of default and non-default cells that overcomes the above described shortcomings of the prior art.